The present invention relates to interface circuits, and more particularly, to interface circuits utilizing phase locked loops to control the flow of data between electronic systems.
The ever increasing demand for information has resulted in an ever increasing demand on electronic circuits and systems to increase information processing abilities. One factor that can be critical to information processing speeds is the rate at which information is transferred between different elements of a system. FIG. 1 illustrates two electronic system elements 100 and 120, which are coupled together by a data communication bus 110. Each system element 100 and 120 may perform particular, and possibly unique, functions executed by cores 101 and 121, respectively. Many electronic system elements may require interaction with one or more other system elements to perform their functions. Interfaces 102 and 122 may be included to perform such interactions over communication bus 110. However, as the information processing speeds of the cores are increased, the speed of the interfaces must also increase to support the increased demands of the cores. Accordingly, improved interface circuit techniques are desirable.
One example of an information processing system in which information is transferred between different system elements is a computer system. Two factors central to increasing information processing capabilities in a computer system are the ability to quickly execute specific instructions, for example, in a central processing unit (“CPU”), and the ability to store large amounts of data that may be processed by the CPU. The last two decades have seen explosive growths in both the processing power of central processing units and the storage capacity of data storage elements such as hard disk drives and random access memories (“RAM”).
Unfortunately, breakthroughs in these areas have also created challenging problems for electronic circuit and system designers. Namely, increased processing power and storage capacity has led to bottlenecks in transferring data between processors and memories. This problem is illustrated in FIG. 2, which shows processor 200 coupled to memory units 221–224 over a bus 220. Processor 200 may be an integrated circuit processor including a CPU core 210, a memory interface 230, and a plurality of subsystem units 241–245. Contemporary CPU cores typically run at very high frequencies, thereby executing large numbers of instructions every second. Instructions and data may be stored external to the processor 200, and thus, a large amount of information may be transferred to and/or from the memories 221–224 over bus 220 every second. Accordingly, as processors obtain ever increasing speeds, and as memories store ever increasing amounts of information utilized by the processors, there is an ever increasing demand placed on the memory interface 230 and bus 220 to meet the speed requirements.
Accordingly, it is desirable to have interface circuits that can transfer data at very high speeds, and in particular, it is desirable to have an interface circuit that can transfer data between a memory and processor at very high speeds.